1. Field of the Invention
The present invention relates to a complementary metal-oxide semiconductor CMOS, and more particularly, to a bipolar junction transistor BJT for compatible high gain gated lateral BJT and more quality device.
2. Description of the Prior Art
Recently, demand for semiconductor devices has rapidly increased owing to widespread use of integrated electronic circuit. In particularly, static random access memory (SRAM) has become a basic and elementary component used in integrated circuits (ICs), such as semiconductor memory devices. More particularly, as more than hundreds or thousands of electrical components are integrated into the ICs, a means for scaling down the dimension of the SRAM and reducing fabrication cost has become imperative.
The conventional CMOS SRAM cell essentially consists of a pair of cross-coupled inverters as the storage flip-flop or latch, and a pair of passes transistors as the access devices for data transfer into and out of the cell. Thus, a total of six Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or four MOSFETs plus two very high resistance load devices are required for implementing a conventional CMOS SRAM cell. However, to achieve high packing density, it is the usual practice to reduce the number of the devices needed for realizing a CMOS SRAM cell or the number of the devices for performing the Write/Read operation. Especially for the case of very high resistance load devices, increased process complexity, extra masks, and high fabrication cost are required for forming the undoped polysilicon layers or the Thin Film Transistor (TFT) on the oxide and thus saving the chip area; however, the corresponding product yield is not high. Therefore, more efforts are needed to further reduce the areas occupied by the chip while improving the production yield.
In the realm of microwave transistors, both bipolar and field effect transistors, higher frequency performance has required narrower and narrower line width. Bipolar IC technology has traditionally been the choice technology for high-speed application. This is partly due to the face that in this technology transit time is determined by the base width of the bipolar device. And the base width not being determined by lithography as is the case with the channel length of MOS devices, but rather by the difference between the impurity diffusion profiles of the emitter and base. In the BJT device structure, a reduction in line width corresponding reduction in the overall bases area. With the overall objective of reduction of capacitance between the junctions, in particular the emitter base junction, the result is shorter emitter base charging times, as well as a reduced transit time across the base. Time translates into an increase in overall device switching speeds and frequency characteristics.
The single material BJT, traditionally silicon, has been the choice technology for high-speed application. This is due in part to the fact that this technology enables transit times that are determined by the base width of the bipolar device.
Designer needs to use BJT in Bandgap Reference and Voltage Regulator circuits. It is more important to make BJT fabrication on CMOS chip. Vertical PNP (P.sup.+ /N-well/P-sub) is used as a BJT compatible with current CMOS technology. Due to higher well concentration is need when shrinking device gate length, vertical BJT gain (p) is getting smaller. Table 1 (Appendix) shows BJT current gain in three different generation technologies.
For the foregoing reasons, there is a need for a method forming higher BJT gain in deep sub-quarter micro CMOS technology. Appendix:
TABLE 1 Vertical PNP .beta. gain in different technology N well X.sub.j P.sup.+ X.sub.j Rs-N well Vertical Technology (.mu.m) (.mu.m) (.OMEGA./square) PNP .beta. gain 0.45 2.7 0.25 724 5 0.35 2.9 0.18 700 3.5 0.25 1.8 0.18 400 2.1